Integration of high performance submicron CMOS and dual-poly non-volatile memory devices using a third polysilicon layer

ABSTRACT

An apparatus and method for integrating a submicron CMOS device and a non-volatile memory, wherein a thermal oxide layer is formed over a semiconductor substrate and a two layered polysilicon non-volatile memory device formed thereon. A portion of the thermal oxide is removed by etching, a thin gate oxide and a third layer of polysilicon having a submicron depth is deposited onto the etched region. The layer of polysilicon is used as the gate for the submicron CMOS device. In so doing a submicron CMOS device may be formed without subjecting the device to the significant re-oxidation required in formation processes for dual poly non-volatile memory devices such as EPROMs and EEPROMs, and separate device optimization is achieved.

TECHNICAL FIELD

The present invention pertains to semiconductor devices. Specifically,the present invention pertains to the integration of submicron CMOSdevices with non-volatile memory devices.

BACKGROUND ART

Erasable programmable read only memories, known as EPROMs, andelectrically erasable programmable read only memories, known as EEPROMs,are well known "floating gate" devices of the art. Typically, thesedouble layer polysilicon non-volatile memory devices are programmed andaccessed using a separate device which is electrically coupled to thememory device. In the past, such programming and accessing has beenaccomplished using a transistor formed during the formation of thememory device. That is, the formation of the transistor was incorporatedinto the manufacturing process flow of the memory device. Specifically,as the second layer of polysilicon was deposited to form the memorycell, the polysilicon was also deposited onto a separate region of thesubstrate. A transistor was then formed in that separate region havingthe second layer of polysilicon as one of the gates of the device.Incorporating the formation of the transistor into the manufacturingprocess flow was considered to be advantageous in that it simplified themanufacturing processes required in the formation of the devices.

Accessing the floating gate device using a high performance submicronsCMOS transistor would be especially beneficial due to the high speed atwhich the submicron CMOS device operates. However, severalincompatibilities exist which inhibit integrating the formation ofsubmicron CMOS devices, such as high performance N-channel and P-channeltransistors, with the manufacturing processes used to form double layerpolysilicon non-volatile memory devices such as EPROMs and EEPROMs.

Floating gate devices, such as EPROMs and EEPROMs, require significantoxidation after the deposition of each of the polysilicon layers formingthese devices. Multiple poly re-oxidations are necessary to achieveadequate charge retention characteristics. Unfortunately, submicron CMOSdevices experience significant transconductance and reliabilitydegradation when exposed to excessive poly re-oxidation. As a result,performance of submicron CMOS devices exposed to dual-poly formationprocesses is prohibitively reduced. Specifically, as submicronpolysilicon gates are exposed to repeated oxidation, the edges of thegates tend to lift from the substrate due to oxidation of the gateedges. This decouples the gate from the channel region. As a result,gain degradation and hot electron reliability problems occur.Additionally, the re-oxidation thermal cycle causes dopant diffusion ofthe channel's voltage adjust implant.

Furthermore, the operation of dual-poly non-volatile memory devices isoften incompatible with the use of high performance submicron CMOSdevices. EPROMs and EEPROMs frequently require relatively highprogramming voltages of 12-18 volts. Such voltages are incompatible withthin gate oxides and lower diode breakdowns found in submicron CMOSdevices. Submicron CMOS devices typically have thin gate oxidethicknesses of less than 200 angstroms. A gate oxide of less than 200angstroms, however, has an intrinsic breakdown of approximately 15volts. Therefore, the programming voltages utilized in dual-polynon-volatile memory elements essentially destroy high performancesubmicron CMOS devices.

Therefore it is an object of the present invention to successfullyintegrate the formation and use of high performance submicron CMOSdevices with the manufacture and operation of dual-poly non-volatilememory devices.

SUMMARY OF THE INVENTION

This object has been achieved by depositing a third layer of polysiliconassociated with a non-volatile memory device as one of the gates of ahigh performance submicron CMOS device. This is done in a manner whichdecouples the processing for the high performance CMOS device from theprocessing for the non-volatile memory device allowing for separateoptimization of the two device types. We form a layer of thermal oxideover a dual-poly non-volatile memory device and over the portion of thesurface of the semiconductor substrate on which the high performanceCMOS device is to be formed. The thermal oxide is then removed from theactive area on the substrate where the high performance submicron CMOSdevice is to be formed.

A thin gate oxide is formed over the active area, and a thresholdvoltage adjust implant is performed. A third layer of polysilicon isthen deposited over the non-volatile memory device and the surface ofthe semiconductor substrate. The third layer of polysilicon is doped andselectively removed from the surface of the semiconductor substrate suchthat the doped layer of polysilicon is removed from everywhere on thesubstrate except for the active region where the submicron device gatesare to be formed.

A high performance submicron CMOS device having a source, drain andgate, is then formed using the portion of the doped polysilicon layerremaining in the active region as a gate. Metallized contacts are madeto the submicron CMOS device, and the device is covered with aprotective coating.

Because the devices are formed at separate times, separate optimizationof dual-poly non-volatile memory devices and high performance submicronCMOS devices is possible. Additionally, the present invention allows thesubmicron CMOS device to be decoupled from the source and draindiffusion cycles required to achieve higher junction breakthroughvoltages in non-volatile memory devices. Furthermore, the separateoptimization can be achieved without compromising the characteristics orreliability of either of the devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-E are side sectional views of the steps used in the integrationof the high performance submicron CMOS device and the dual-polynon-volatile memory device in accord with the present invention.

FIG. 2 is a circuit diagram of the integrated high performance submicronCMOS device and the dual-poly non-volatile memory device in accord withthe present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

With reference to FIG. 1A, a cross-sectional view of the starting stepin the formation of the present invention is shown. A p-doped siliconsubstrate 20 containing a p-doped well 22 and having an EPROM 24 formedthereon is shown. Although the semiconductor substrate 20 is formed ofsilicon in the preferred embodiment, any other suitable semiconductormaterial may be used. Additionally, the substrate 20 may also have adifferent conductivity type if desired. Further, although an EPROM 24 isused in the preferred embodiment, an EEPROM is also compatible with themethods of the present invention.

The EPROM 24 is formed of two stacked and aligned layers of polysilicon,26 and 28, formed over a high voltage source 30 and drain 32, andseparated from the substrate 24 by a thick gate oxide layer 33. The twolayers of polysilicon, 26 and 28, are separated by an insulatingdielectric layer 34, and are subjected to re-oxidation. Afterre-oxidation of the two polysilicon layers, 26 and 28, a layer ofthermal oxide 36 is formed over the EPROM 24 and the silicon substrate20. In the preferred embodiment of the present invention, the thermaloxide 36 is formed to a depth of approximately 200 angstroms.

As shown in FIG. 1B, the thermal oxide layer 36 is then removed from aregion 38 of the silicon substrate 20 above the p-doped well 22. In sodoing, the thermal oxide 36 is cleared from the active region 38 of thesilicon substrate 20 where the thin gate oxide layer of the highperformance submicron CMOS transistor is to be formed. In the preferredembodiment, the thermal oxide 36 is removed using a wet HF etch,however, any of the numerous etching techniques well known in the artare suitable.

Referring now to FIG. 1C, a thin gate oxide layer 40 is formed in theactive region 38 of the silicon substrate 20. The gate oxide 40 istypically formed to a thickness of approximately 100 to 150 angstroms.In forming the thin gate oxide 40, additional re-oxidation also occursin the two polysilicon layers, 26 and 28, of the EPROM 24. As a resultthe polysilicon layers, 26 and 28, are oxidized to a final thickness ofabout 500 angstroms. After the formation of the thin gate oxide 40, anenhancement implant 42 is made into the p-doped region 22 of the siliconsubstrate 20. Enhancement implant 42 is a light dose implant of BF₂, orany other well known dopant, which is used to adjust the thresholdvoltage of the high performance submicron CMOS transistor.

With reference to FIG. 1D, a third layer of polysilicon 44 is depositedover the surface of the silicon substrate. As a result, both the thingate oxide 40 and the EPROM 24 are covered by the layer of polysilicon44. The polysilicon 44 is typically deposited to a thickness of about2000 to 5000 angstroms. The third layer of polysilicon 44 is then dopedwith an n-type dopant such as phosphorous, producing an n⁺ typeconductivity in the third polysilicon layer 44.

As shown in FIG. 1E, the third doped layer of polysilicon 44 is thenremoved from everywhere on the silicon substrate 20 except for the areaabove the thin gate oxide 40. In so doing, a gate region 46 for the highperformance submicron CMOS transistor is formed. In forming gate 46 ofthe high performance submicron CMOS transistor from third polysiliconlayer 44, the submicron CMOS device is effectively decoupled from theEPROM device 24, allowing for separate optimization of the two devices.As a result, the transistor is not adversely affected by the highprogramming voltages, 12-20 volts, necessary for the EPROM 24. Anadditional etch step is then performed in order to remove any residualpolysilicon that may have been deposited onto the sidewalls of the firsttwo polysilicon layers, 26 and 28, during the deposition of thesubmicron third polysilicon layer 44.

The formation of the submicron CMOS transistor is completed byimplanting a low voltage source 48 and drain 50, and forming metallizedcontacts, not shown, to low voltage source 48 and drain 50, and gate 46.The device is then covered with a protective coating. In the preferredembodiment of the present invention, an N-channel type high performancesubmicron CMOS transistor is formed. However, the methods of the presentinvention would also apply to the formation of a P-channel type highperformance submicron transistor, by forming the transistor in ann-doped well containing a p-doped source and drain region.

Referring now to FIG. 2, a circuit diagram illustrating the integrationof the submicron CMOS device and EPROM 24 of the present invention isshown. EPROM 24 and high performance sub-micron CMOS transistor 60, usedto access EPROM 24, are coupled in series between column line 62 andground line 64. The drain terminal of submicron CMOS transistor 60 isconnected to column line 62 through metal contact 66. The gate oftransistor 60 is coupled to access line 68. Additionally, the gate ofEPROM 24 is coupled to a read line 70. In so doing, high speed submicronCMOS transistor 60, may be used to access EPROM 24.

Referring again to FIG. 1, the present invention as described above hasseveral advantages over the prior art. The third polysilicon layer 44allows the high performance submicron CMOS transistor to be formedwithout having to be subjected to the significant re-oxidations requiredin the formation of the EPROM 24.

By using a submicron CMOS transistor, the EPROM can be accessed and readat higher speeds than were possible with the standard transistors of theprior art. Additionally, the third layer of polysilicon 44 decouples thesubmicron CMOS transistor and the EPROM 24 such that they may beseparately optimized. As a result, both of the devices can be utilizedwithout compromising the characteristics or reliability of the other.

Additionally, the two devices can be manufactured in the same processflow, thereby reducing the manufacturing cost of the system, byeliminating manufacturing steps, while simultaneously improving theyield and reliability of the manufacturing processes.

We claim:
 1. A method for forming .Iadd.each of a plurality ofnon-volatile memory cells in an array of such cells, each of saidnon-volatile memory cells including .Iaddend.a submicron .Iadd.CMOS.Iaddend.transistor adjacent to a non-volatile memory.Iadd.floating-gate .Iaddend.transistor.Iadd., said method.Iaddend.comprising the steps of:(.Iadd.a) .Iaddend.providing asemiconductor substrate of a first conductivity type.[.,.].; (.Iadd.b).Iaddend.forming a non-volatile memory .Iadd.floating-gate.Iaddend.transistor on a first region of said semiconductorsubstrate.[.,.].; including(.Iadd.i) .Iaddend.forming a first gate oxidelayer on said substrate, (.Iadd.ii) .Iaddend.forming a first polysiliconlayer on said first gate oxide layer, (.Iadd.iii) .Iaddend.forming asecond gate oxide layer on said .Iadd.first .Iaddend.polysilicon layer,(.Iadd.iv) forming a second polysilicon layer on said second gate oxidelayer,.Iaddend. (.Iadd.v) .Iaddend.selectively etching said .Iadd.firstand second .Iaddend.gate oxide and polysilicon layers to leave a pair ofpolysilicon gates stacked above a section of said first region, saidgates separated from each other by said second gate oxide layer andseparated from said substrate by said first gate oxide layer, .Iadd.and.Iaddend. (.Iadd.vi) .Iaddend.forming doped .Iadd.source and drain.Iaddend.regions of a second conductivity type in said first regionproximate to said pair of gates, (.Iadd.c) .Iaddend.forming a thermaloxide layer over said non-volatile memory .[.device.]..Iadd.floating-gate transistor .Iaddend.and said semiconductorsubstrate, .Iadd.said thermal oxide layer being formed to a firstthickness which is a predetermined fraction of a desired final thermaloxide thickness, wherein said final thickness is sufficient to withstanda programming voltage of at least 12 volts;.Iaddend. (.Iadd.d)completely .Iaddend.removing said thermal oxide .Iadd.layer.Iaddend.from a second region of said substrate .Iadd.such that thesurface of said second region is left bare.Iaddend., said second region.Iadd.adjacent to but .Iaddend.separated from said first region by afield oxide region.[.,.].; (.Iadd.e) .Iaddend.forming a third gate oxidelayer over said .Iadd.first and .Iaddend.second .[.region.]..Iadd.regions .Iaddend.of said substrate, .Iadd.said third gate oxidelayer being formed to a second thickness such that the sum of said firstand second thicknesses is substantially equal to said desired finalthermal oxide thickness;.Iaddend. (.Iadd.f) .Iaddend.forming a thirdlayer of polysilicon over said non-volatile memory .[.device.]..Iadd.floating-gate transistor .Iaddend.and said third gate oxidelayer.[.,.].; (.Iadd.g) .Iaddend.selectively removing said third layerof polysilicon such that said third layer of polysilicon is removed fromeverywhere except for atop a portion .Iadd.of .Iaddend.said secondregion.[.,.].; (.Iadd.h) .Iaddend.forming a submicron CMOS transistor,including implanting dopants of said second conductivity type into saidsecond region of said substrate adjacent to said portion under saidthird layer of polysilicon.[.,.]. .Iadd.to form source and drain regionsof said submicron CMOS transistor;.Iaddend. (.Iadd.i) .Iaddend.formingmetallized contacts to said submicron CMOS transistor and saidnon-volatile memory .Iadd.floating-gate .Iaddend.transistor, .Iadd.saidcontacts coupling the drain of said non-volatile memory floating-gatetransistor to the source of said submicron CMOS transistor, coupling thedrain of said submicron CMOS transistor to a bitline of the array,coupling the source of said non-volatile memory floating-gate transistorto a ground potential, coupling the third layer of polysilicon forming acontrol gate of said submicron CMOS transistor to an access line, andcoupling the second polysilicon layer forming a control gate of saidnon-volatile memory floating-gate transistor to a read line,.Iaddend.and (.Iadd.j) .Iaddend.covering said semiconductor substrateincluding said submicron CMOS transistor and said non-volatile memory.Iadd.floating-gate .Iaddend.transistor with a protective coating. 2.The method as recited in claim 1 further comprising:oxidizing said pairof .Iadd.polysilicon .Iaddend.gates, prior to forming said thermal oxidelayer over said non-volatile memory .[.device.]. .Iadd.floating-gatetransistor.Iaddend., whereby charge retention characteristics of said.Iadd.polysilicon .Iaddend.gates are enhanced without impairingperformance of said submicron CMOS transistor.
 3. The method as recitedin claim 1 wherein forming said non-volatile memory .[.trnasistor.]..Iadd.floating-gate transistor .Iaddend.further comprises the steps offorming an EPROM transistor.
 4. The method as recited in claim 1 whereinforming said non-volatile memory .Iadd.floating-gate .Iaddend.transistorfurther comprises the steps of forming an EEPROM transistor.
 5. Themethod as recited in claim 1 wherein forming said submicron CMOStransistor comprises the steps of forming a submicron CMOS N-channeltransistor.
 6. The method as recited in claim 1 wherein forming saidsubmicron CMOS transistor comprises the steps of forming a submicronCMOS P-channel transistor.
 7. The method as recited in claim 1 whereinsaid metallized contacts formed to said submicron CMOS transistor areformed contacting said source, drain and gate of said .Iadd.submicronCMOS .Iaddend.transistor.
 8. The method as recited in claim 1 whereinsaid thermal oxide .Iadd.layer .Iaddend.is formed to a depth ofapproximately 300 angstroms over said non-volatile memory.Iadd.floating-gate .Iaddend.transistor.Iadd., and said third gate oxidelayer brings the oxide over said non-volatile memory floating-gatetransistor to a desired final thickness of approximately 500angstroms.Iaddend..
 9. The method as recited in claim 1 wherein saidthermal oxide is removed from said first region using a wet HF etch. 10.The method as recited in claim 1 wherein said .Iadd.third .Iaddend.gateoxide layer is formed to a .[.depth.]. .Iadd.thickness .Iaddend.that isless than that of said first gate oxide layer.
 11. The method as recitedin claim 1 wherein said third gate oxide layer is formed to a depth ofbetween 100 and 150 angstroms. .[.12. The method as recited in claim 1further including forming a plurality of said non-volatile memorytransistors..]..[.13. The method as recited in claim 1 further includingforming a plurality of said submicron CMOS transistors..].14. A methodof forming a .Iadd.non-volatile .Iaddend.CMOS memory cell .Iadd.for usein the formation of an array of non-volatile memory cells, said method.Iaddend.comprising:(.Iadd.a) .Iaddend.forming a floating gate CMOSmemory transistor .Iadd.in a semiconductor substrate.Iaddend.,including(.Iadd.i) .Iaddend.forming a first gate oxide layer on saidsubstrate, (.Iadd.ii) .Iaddend.forming a first polysilicon layer on saidfirst gate oxide layer, (.Iadd.iii) .Iaddend.forming a second gate oxidelayer on said first polysilicon layer, (.Iadd.iv) forming a secondpolysilicon layer on said second gate oxide layer, and.Iaddend.(.Iadd.v) selectively .Iaddend.etching said .Iadd.first and second.Iaddend.polysilicon layers and said .Iadd.first and second.Iaddend.gate oxide layers to leave a stack of said layers atop saidsubstrate between a .Iadd.first .Iaddend.source region and a .Iadd.first.Iaddend.drain region, (.Iadd.b) .Iaddend.subsequently forming a highperformance CMOS transistor adjacent to said memory transistor,including(.Iadd.i) .Iaddend.forming a third gate oxide .Iadd.on acompletely bare region of a surface of .Iaddend.layer on said substrate.Iadd.that is adjacent to but .Iaddend.spaced apart from said.Iadd.floating gate CMOS .Iaddend.memory transistor by a field oxideregion, .Iadd.said third gate oxide layer also being formed over saidfloating gate CMOS memory transistor,.Iaddend. (.Iadd.ii).Iaddend.forming a third polysilicon layer on said third gate oxidelayer, (.Iadd.iii) selectively .Iaddend.etching said third polysiliconlayer to leave a submicron gate separated from said .Iadd.floating gateCMOS .Iaddend.memory transistor by a field oxide region, and (.Iadd.iv).Iaddend.doping said substrate proximate to said submicron gate .Iadd.toform a second source region and a second drain region.Iaddend., and(.Iadd.c) forming metallized contacts coupling said second source regionto said first drain region .Iaddend.such that said high performance.Iadd.CMOS .Iaddend.transistor can electrically communicate with said.Iadd.floating gate CMOS .Iaddend.memory transistor.
 15. In a method offorming a .Iadd.non-volatile .Iaddend.CMOS memory cell with athree-layer polysilicon process, the improvement comprising:(.Iadd.a).Iaddend.forming a floating gate CMOS memory transistor in a first timeinterval, including(.Iadd.i) .Iaddend.forming a first gate oxide layeron a substrate, (.Iadd.ii) .Iaddend.forming a first polysilicon layer onsaid first gate oxide layer, (.Iadd.iii) .Iaddend.forming a second gateoxide layer on said first polysilicon layer, (.Iadd.iv) .Iaddend.forminga second polysilicon layer on said second gate oxide layer,.Iadd.and.Iaddend. (.Iadd.v) selectively .Iaddend.etching said.Iadd.first and second .Iaddend.polysilicon and gate oxide layers toleave a sense gate disposed above a floating gate disposed above achannel between a source region and a drain region of said substrate,.[.and.]. (.Iadd.b) .Iaddend.forming a high performance CMOS transistorin a second time interval, after the first time interval,including(.Iadd.i) .Iaddend.forming a third gate oxide layer on a.Iadd.bare .Iaddend.section of said substrate adjacent to said.Iadd.floating gate CMOS .Iaddend.memory transistor, said sectionseparated from said .Iadd.floating gate CMOS .Iaddend.memory .[.cell.]..Iadd.transistor .Iaddend.by a field oxide region, (.Iadd.ii).Iaddend.forming a third polysilicon layer on said third gate oxidelayer, (.Iadd.iii) selectively .Iaddend.etching said third polysiliconlayer to leave a gate atop said section, and (.Iadd.iv) .Iaddend.dopingsaid section around said gate to form electrically conductive regions,.Iadd.and.Iaddend. (.Iadd.c) forming metallic contacts coupling one ofsaid electrically conductive regions of said high performance CMOStransistor to said drain region of said floating gate CMOS memorytransistor .Iaddend.such that said high performance .Iadd.CMOS.Iaddend.transistor can electrically communicate with said.Iadd.floating gate CMOS .Iaddend.memory transistor.